- Generated by
1.9.8
|
infix
A JIT-Powered FFI Library for C
|
Common register definitions and instruction encodings for the RISC-V RV64GC architecture. More...
#include <stdint.h>Go to the source code of this file.
Macros | |
| #define | RV_OP_LOAD 0x03U |
| #define | RV_OP_OP_IMM 0x13U |
| #define | RV_OP_OP_IMM_32 0x1BU |
| #define | RV_OP_AUIPC 0x17U |
| #define | RV_OP_STORE 0x23U |
| #define | RV_OP_OP 0x33U |
| #define | RV_OP_LUI 0x37U |
| #define | RV_OP_BRANCH 0x63U |
| #define | RV_OP_JALR 0x67U |
| #define | RV_OP_JAL 0x6FU |
| #define | RV_OP_FP 0x53U |
| #define | RV_OP_SYSTEM 0x73U |
| #define | RV_OP_FLOAD 0x07U |
| #define | RV_OP_FSTORE 0x27U |
| #define | RV_F3_ADD_SUB 0x0U |
| #define | RV_F3_SLL 0x1U |
| #define | RV_F3_SLT 0x2U |
| #define | RV_F3_SLTU 0x3U |
| #define | RV_F3_XOR 0x4U |
| #define | RV_F3_SR 0x5U |
| #define | RV_F3_OR 0x6U |
| #define | RV_F3_AND 0x7U |
| #define | RV_F3_LD 0x3U |
| #define | RV_F3_LW 0x2U |
| #define | RV_F3_LH 0x1U |
| #define | RV_F3_LB 0x0U |
| #define | RV_F3_LBU 0x4U |
| #define | RV_F3_LHU 0x5U |
| #define | RV_F3_LWU 0x6U |
| #define | RV_F3_FLD 0x3U |
| #define | RV_F3_FLW 0x2U |
| #define | RV_F3_FLH 0x1U |
| #define | RV_F3_BEQ 0x0U |
| #define | RV_F3_BNE 0x1U |
| #define | RV_F3_BLT 0x4U |
| #define | RV_F3_BGE 0x5U |
| #define | RV_F3_BLTU 0x6U |
| #define | RV_F3_BGEU 0x7U |
| #define | RV_F7_ADD 0x00U |
| #define | RV_F7_SUB 0x20U |
| #define | RV_F7_SLL 0x00U |
| #define | RV_F7_SRL 0x00U |
| #define | RV_F7_SRA 0x20U |
| #define | RV_F6_SLLI 0x00U |
| #define | RV_F6_SRLI 0x00U |
| #define | RV_F6_SRAI 0x10U |
| #define | RV_F7_FMV_X_S 0x70U |
| #define | RV_F7_FMV_S_X 0x78U |
| #define | RV_F7_FMV_X_D 0x71U |
| #define | RV_F7_FMV_D_X 0x79U |
| #define | RV_F7_FMV_X_H 0x72U |
| #define | RV_F7_FMV_H_X 0x7AU |
| #define | RV_F7_FSGNJ_S 0x10U |
| #define | RV_F7_FSGNJ_D 0x11U |
| #define | RV_FCVT_RM_RNE 0x0U |
| #define | RV_F7_FCVT_S_D 0x20U |
| #define | RV_F7_FCVT_D_S 0x21U |
| #define | RV_RS2_FCVT_D_S 0x00U |
| #define | RV_RS2_FCVT_S_D 0x01U |
| #define | RV_RS1_SHIFT 15U |
| #define | RV_RS2_SHIFT 20U |
| #define | RV_RD_SHIFT 7U |
| #define | RV_FUNCT3_SHIFT 12U |
| #define | RV_CTX_TARGET_REG X_S1_REG |
| #define | RV_CTX_RET_REG X_S2_REG |
| #define | RV_CTX_ARGS_REG X_S3_REG |
| #define | RV_SCRATCH0_REG X_T0_REG |
| #define | RV_SCRATCH1_REG X_T1_REG |
| #define | RV_SCRATCH2_REG X_T2_REG |
| #define | RV_SCRATCH3_REG X_T3_REG |
Enumerations | |
| enum | riscv_gpr { X_ZERO_REG = 0 , X_RA_REG , X_SP_REG , X_GP_REG , X_TP_REG , X_T0_REG , X_T1_REG , X_T2_REG , X_S0_REG , X_S1_REG , X_A0_REG = 10 , X_A1_REG , X_A2_REG , X_A3_REG , X_A4_REG , X_A5_REG , X_A6_REG , X_A7_REG , X_S2_REG = 18 , X_S3_REG , X_S4_REG , X_S5_REG , X_S6_REG , X_S7_REG , X_S8_REG , X_S9_REG , X_S10_REG , X_S11_REG , X_T3_REG = 28 , X_T4_REG , X_T5_REG , X_T6_REG } |
| enum | riscv_fpr { F_FT0_REG = 0 , F_FT1_REG , F_FT2_REG , F_FT3_REG , F_FT4_REG , F_FT5_REG , F_FT6_REG , F_FT7_REG , F_FS0_REG = 8 , F_FS1_REG , F_FA0_REG = 10 , F_FA1_REG , F_FA2_REG , F_FA3_REG , F_FA4_REG , F_FA5_REG , F_FA6_REG , F_FA7_REG , F_FS2_REG = 18 , F_FS3_REG , F_FS4_REG , F_FS5_REG , F_FS6_REG , F_FS7_REG , F_FS8_REG , F_FS9_REG , F_FS10_REG , F_FS11_REG , F_FT8_REG = 28 , F_FT9_REG , F_FT10_REG , F_FT11_REG } |
Common register definitions and instruction encodings for the RISC-V RV64GC architecture.
Copyright (c) 2026 Sanko Robinson
This source code is dual-licensed under the Artistic License 2.0 or the MIT License. You may choose to use this code under the terms of either license.
SPDX-License-Identifier: (Artistic-2.0 OR MIT)
The documentation blocks within this file are licensed under the Creative Commons Attribution 4.0 International License (CC BY 4.0).
SPDX-License-Identifier: CC-BY-4.0
| #define RV_CTX_ARGS_REG X_S3_REG |
| #define RV_CTX_RET_REG X_S2_REG |
| #define RV_CTX_TARGET_REG X_S1_REG |
| #define RV_F3_ADD_SUB 0x0U |
| #define RV_F3_AND 0x7U |
| #define RV_F3_BEQ 0x0U |
| #define RV_F3_BGE 0x5U |
| #define RV_F3_BGEU 0x7U |
| #define RV_F3_BLT 0x4U |
| #define RV_F3_BLTU 0x6U |
| #define RV_F3_BNE 0x1U |
| #define RV_F3_FLD 0x3U |
| #define RV_F3_FLH 0x1U |
| #define RV_F3_FLW 0x2U |
| #define RV_F3_LB 0x0U |
| #define RV_F3_LBU 0x4U |
| #define RV_F3_LD 0x3U |
| #define RV_F3_LH 0x1U |
| #define RV_F3_LHU 0x5U |
| #define RV_F3_LW 0x2U |
| #define RV_F3_LWU 0x6U |
| #define RV_F3_OR 0x6U |
| #define RV_F3_SLL 0x1U |
| #define RV_F3_SLT 0x2U |
| #define RV_F3_SLTU 0x3U |
| #define RV_F3_SR 0x5U |
| #define RV_F3_XOR 0x4U |
| #define RV_F6_SLLI 0x00U |
| #define RV_F6_SRAI 0x10U |
| #define RV_F6_SRLI 0x00U |
| #define RV_F7_ADD 0x00U |
| #define RV_F7_FCVT_D_S 0x21U |
| #define RV_F7_FCVT_S_D 0x20U |
| #define RV_F7_FMV_D_X 0x79U |
| #define RV_F7_FMV_H_X 0x7AU |
| #define RV_F7_FMV_S_X 0x78U |
| #define RV_F7_FMV_X_D 0x71U |
| #define RV_F7_FMV_X_H 0x72U |
| #define RV_F7_FMV_X_S 0x70U |
| #define RV_F7_FSGNJ_D 0x11U |
| #define RV_F7_FSGNJ_S 0x10U |
| #define RV_F7_SLL 0x00U |
| #define RV_F7_SRA 0x20U |
| #define RV_F7_SRL 0x00U |
| #define RV_F7_SUB 0x20U |
| #define RV_FCVT_RM_RNE 0x0U |
| #define RV_FUNCT3_SHIFT 12U |
| #define RV_OP_AUIPC 0x17U |
| #define RV_OP_BRANCH 0x63U |
| #define RV_OP_FLOAD 0x07U |
| #define RV_OP_FP 0x53U |
| #define RV_OP_FSTORE 0x27U |
| #define RV_OP_JAL 0x6FU |
| #define RV_OP_JALR 0x67U |
| #define RV_OP_LOAD 0x03U |
| #define RV_OP_LUI 0x37U |
| #define RV_OP_OP 0x33U |
| #define RV_OP_OP_IMM 0x13U |
| #define RV_OP_OP_IMM_32 0x1BU |
| #define RV_OP_STORE 0x23U |
| #define RV_OP_SYSTEM 0x73U |
| #define RV_RD_SHIFT 7U |
| #define RV_RS1_SHIFT 15U |
| #define RV_RS2_FCVT_D_S 0x00U |
| #define RV_RS2_FCVT_S_D 0x01U |
| #define RV_RS2_SHIFT 20U |
| #define RV_SCRATCH0_REG X_T0_REG |
| #define RV_SCRATCH1_REG X_T1_REG |
| #define RV_SCRATCH2_REG X_T2_REG |
| #define RV_SCRATCH3_REG X_T3_REG |
| enum riscv_fpr |
| enum riscv_gpr |
1.9.8