abi_riscv64_common.h

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#pragma once
#include <stdint.h>
typedef enum {
    X_ZERO_REG = 0,  
    X_RA_REG,        
    X_SP_REG,        
    X_GP_REG,        
    X_TP_REG,        
    X_T0_REG,        
    X_T1_REG,        
    X_T2_REG,        
    X_S0_REG,        
    X_S1_REG,        
    X_A0_REG = 10,   
    X_A1_REG,        
    X_A2_REG,        
    X_A3_REG,        
    X_A4_REG,        
    X_A5_REG,        
    X_A6_REG,        
    X_A7_REG,        
    X_S2_REG = 18,   
    X_S3_REG,        
    X_S4_REG,        
    X_S5_REG,        
    X_S6_REG,        
    X_S7_REG,        
    X_S8_REG,        
    X_S9_REG,        
    X_S10_REG,       
    X_S11_REG,       
    X_T3_REG = 28,   
    X_T4_REG,        
    X_T5_REG,        
    X_T6_REG         
} riscv_gpr;
typedef enum {
    F_FT0_REG = 0,   
    F_FT1_REG,       
    F_FT2_REG,       
    F_FT3_REG,       
    F_FT4_REG,       
    F_FT5_REG,       
    F_FT6_REG,       
    F_FT7_REG,       
    F_FS0_REG = 8,   
    F_FS1_REG,       
    F_FA0_REG = 10,  
    F_FA1_REG,       
    F_FA2_REG,       
    F_FA3_REG,       
    F_FA4_REG,       
    F_FA5_REG,       
    F_FA6_REG,       
    F_FA7_REG,       
    F_FS2_REG = 18,  
    F_FS3_REG,       
    F_FS4_REG,       
    F_FS5_REG,       
    F_FS6_REG,       
    F_FS7_REG,       
    F_FS8_REG,       
    F_FS9_REG,       
    F_FS10_REG,      
    F_FS11_REG,      
    F_FT8_REG = 28,  
    F_FT9_REG,       
    F_FT10_REG,      
    F_FT11_REG       
} riscv_fpr;
// Base opcodes (bits 6:0)
#define RV_OP_LOAD 0x03U       // Loads (lb, lh, lw, ld, lbu, lhu, lwu)
#define RV_OP_OP_IMM 0x13U     // Register-immediate ALU ops (addi, slli, ...)
#define RV_OP_OP_IMM_32 0x1BU  // Register-immediate 32-bit ALU ops (addiw)
#define RV_OP_AUIPC 0x17U      // Add upper immediate to pc
#define RV_OP_STORE 0x23U      // Stores (sb, sh, sw, sd)
#define RV_OP_OP 0x33U         // Register-register ALU ops (add, sub, sll, ...)
#define RV_OP_LUI 0x37U        // Load upper immediate
#define RV_OP_BRANCH 0x63U     // Conditional branches
#define RV_OP_JALR 0x67U       // Jump and link register
#define RV_OP_JAL 0x6FU        // Jump and link
#define RV_OP_FP 0x53U         // Floating-point register ops
#define RV_OP_SYSTEM 0x73U     // System instructions
#define RV_OP_FLOAD 0x07U      // Floating-point loads (flw, fld)
#define RV_OP_FSTORE 0x27U     // Floating-point stores (fsw, fsd)
// funct3 fields (bits 14:12)
#define RV_F3_ADD_SUB 0x0U  // ADDI / ADD / SUB / SLL
#define RV_F3_SLL 0x1U      // SLLI / SLL
#define RV_F3_SLT 0x2U
#define RV_F3_SLTU 0x3U
#define RV_F3_XOR 0x4U
#define RV_F3_SR 0x5U  // SRLI / SRAI / SRL / SRA
#define RV_F3_OR 0x6U
#define RV_F3_AND 0x7U
// funct3 fields for loads/stores
#define RV_F3_LD 0x3U   // LD / SD
#define RV_F3_LW 0x2U   // LW / SW
#define RV_F3_LH 0x1U   // LH / SH
#define RV_F3_LB 0x0U   // LB / SB
#define RV_F3_LBU 0x4U  // LBU (no unsigned store exists)
#define RV_F3_LHU 0x5U  // LHU
#define RV_F3_LWU 0x6U  // LWU
#define RV_F3_FLD 0x3U  // FLD / FSD
#define RV_F3_FLW 0x2U  // FLW / FSW
#define RV_F3_FLH 0x1U  // FLH / FSH (Zfh)
// funct3 fields for branches
#define RV_F3_BEQ 0x0U
#define RV_F3_BNE 0x1U
#define RV_F3_BLT 0x4U
#define RV_F3_BGE 0x5U
#define RV_F3_BLTU 0x6U
#define RV_F3_BGEU 0x7U
// funct7 fields (bits 31:25) for R-type integer ops
#define RV_F7_ADD 0x00U
#define RV_F7_SUB 0x20U
#define RV_F7_SLL 0x00U
#define RV_F7_SRL 0x00U
#define RV_F7_SRA 0x20U
// Shift immediate funct6 (bits 31:26)
#define RV_F6_SLLI 0x00U
#define RV_F6_SRLI 0x00U
#define RV_F6_SRAI 0x10U
// Floating-point move instructions (funct7 selects the operation).
// The RV64 W-level moves transfer between GPRs and single-precision FP registers.
#define RV_F7_FMV_X_S 0x70U  // FMV.X.W: FP(single) -> GPR
#define RV_F7_FMV_S_X 0x78U  // FMV.W.X: GPR -> FP(single)
#define RV_F7_FMV_X_D 0x71U  // FMV.X.D: FP(double) -> GPR
#define RV_F7_FMV_D_X 0x79U  // FMV.D.X: GPR -> FP(double)
#define RV_F7_FMV_X_H 0x72U  // FMV.X.H (Zfh)
#define RV_F7_FMV_H_X 0x7AU  // FMV.H.X (Zfh)
// FP-to-FP moves are the FSGNJ pseudo-instructions (fmv.s rd,rs1 == fsgnj.s rd,rs1,rs1).
#define RV_F7_FSGNJ_S 0x10U  // FSGNJ.S
#define RV_F7_FSGNJ_D 0x11U  // FSGNJ.D
// The 'imm' (rs2) encodings used by the fcvt family to select source/target precision.
// The source precision selects funct7 bit 0: 0 = 32-bit source (FCVT.S.D), 1 = 64-bit source (FCVT.D.S).
#define RV_FCVT_RM_RNE 0x0U    // Round to nearest, ties to even
#define RV_F7_FCVT_S_D 0x20U   // FCVT.S.D: source is double-precision, dest is single
#define RV_F7_FCVT_D_S 0x21U   // FCVT.D.S: source is single-precision, dest is double
#define RV_RS2_FCVT_D_S 0x00U  // rs2 field for FCVT.D.S
#define RV_RS2_FCVT_S_D 0x01U  // rs2 field for FCVT.S.D
// Instruction bit-field helper macros
#define RV_RS1_SHIFT 15U
#define RV_RS2_SHIFT 20U
#define RV_RD_SHIFT 7U
#define RV_FUNCT3_SHIFT 12U
 
// Trampoline register roles (internal to the RISC-V backend).
#define RV_CTX_TARGET_REG X_S1_REG
#define RV_CTX_RET_REG X_S2_REG
#define RV_CTX_ARGS_REG X_S3_REG
#define RV_SCRATCH0_REG X_T0_REG
#define RV_SCRATCH1_REG X_T1_REG
#define RV_SCRATCH2_REG X_T2_REG
#define RV_SCRATCH3_REG X_T3_REG