abi_arm64_common.h File Reference

Common register definitions for the AArch64 (ARM64) architecture. More...

#include <stdint.h>

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Macros
#define	A64_SF_64BIT   (1U << 31)
#define	A64_SF_32BIT   (0U << 31)
#define	A64_V_VECTOR   (1U << 26)
#define	A64_OPC_ADD   (0b00U << 29)
#define	A64_OPC_ADDS   (0b01U << 29)
#define	A64_OPC_SUB   (0b10U << 29)
#define	A64_OPC_SUBS   (0b11U << 29)
#define	A64_OP_ADD_SUB_IMM   (0b0010001U << 24)
#define	A64_OP_ADD_SUB_REG   (0b01011U << 24)
#define	A64_OP_LOGICAL_REG   (0b01010U << 24)
#define	A64_OPCODE_ORR   (0b01U << 29)
#define	A64_OPC_MOVZ   (0b10U << 29)
#define	A64_OPC_MOVK   (0b11U << 29)
#define	A64_OP_MOVE_WIDE_IMM   (0b100101U << 23)
#define	A64_OP_LOAD_STORE_IMM_UNSIGNED   (0b111001U << 24)
#define	A64_LDR_OP   (1U << 22)
#define	A64_OP_LOAD_STORE_PAIR_BASE   (0b101000U << 24)
#define	A64_OPC_STP   (0b00U << 30)
#define	A64_OPC_LDP   (0b01U << 30)
#define	A64_L_BIT_LOAD   (1U << 22)
#define	A64_ADDR_POST_INDEX   (0b01U << 23)
#define	A64_ADDR_PRE_INDEX   (0b11U << 23)
#define	A64_ADDR_SIGNED_OFFSET   (0b10U << 23)
#define	A64_OP_BRANCH_REG   (0b1101011U << 25)
#define	A64_OPC_BR   (0b0000U << 21)
#define	A64_OPC_BLR   (0b0001U << 21)
#define	A64_OPC_RET   (0b0010U << 21)
#define	A64_OP_COMPARE_BRANCH_IMM   (0b011010U << 25)
#define	A64_OPC_CBNZ   (1U << 24)
#define	A64_OP_SYSTEM   (0b11010100U << 25)
#define	A64_OP_BRK   (0b00000000001U << 16)

Enumerations
enum	arm64_gpr {   X0_REG = 0 , X1_REG , X2_REG , X3_REG ,   X4_REG , X5_REG , X6_REG , X7_REG ,   X8_REG , X9_REG , X10_REG , X11_REG ,   X12_REG , X13_REG , X14_REG , X15_REG ,   X16_REG , X17_REG , X18_REG , X19_REG ,   X20_REG , X21_REG , X22_REG , X23_REG ,   X24_REG , X25_REG , X26_REG , X27_REG ,   X28_REG , X29_FP_REG , X30_LR_REG , SP_REG = 31 }
enum	arm64_vpr {   V0_REG = 0 , V1_REG , V2_REG , V3_REG ,   V4_REG , V5_REG , V6_REG , V7_REG ,   V8_REG , V9_REG , V10_REG , V11_REG ,   V12_REG , V13_REG , V14_REG , V15_REG ,   V16_REG , V17_REG , V18_REG , V19_REG ,   V20_REG , V21_REG , V22_REG , V23_REG ,   V24_REG , V25_REG , V26_REG , V27_REG ,   V28_REG , V29_REG , V30_REG , V31_REG }

Detailed Description

Common register definitions for the AArch64 (ARM64) architecture.

Copyright (c) 2025 Sanko Robinson

This source code is dual-licensed under the Artistic License 2.0 or the MIT License. You may choose to use this code under the terms of either license.

SPDX-License-Identifier: (Artistic-2.0 OR MIT)

The documentation blocks within this file are licensed under the Creative Commons Attribution 4.0 International License (CC BY 4.0).

SPDX-License-Identifier: CC-BY-4.0

Macro Definition Documentation

A64_ADDR_POST_INDEX

#define A64_ADDR_POST_INDEX   (0b01U << 23)

A64_ADDR_PRE_INDEX

#define A64_ADDR_PRE_INDEX   (0b11U << 23)

A64_ADDR_SIGNED_OFFSET

#define A64_ADDR_SIGNED_OFFSET   (0b10U << 23)

A64_L_BIT_LOAD

#define A64_L_BIT_LOAD   (1U << 22)

A64_LDR_OP

#define A64_LDR_OP   (1U << 22)

A64_OP_ADD_SUB_IMM

#define A64_OP_ADD_SUB_IMM   (0b0010001U << 24)

A64_OP_ADD_SUB_REG

#define A64_OP_ADD_SUB_REG   (0b01011U << 24)

A64_OP_BRANCH_REG

#define A64_OP_BRANCH_REG   (0b1101011U << 25)

A64_OP_BRK

#define A64_OP_BRK   (0b00000000001U << 16)

A64_OP_COMPARE_BRANCH_IMM

#define A64_OP_COMPARE_BRANCH_IMM   (0b011010U << 25)

A64_OP_LOAD_STORE_IMM_UNSIGNED

#define A64_OP_LOAD_STORE_IMM_UNSIGNED   (0b111001U << 24)

A64_OP_LOAD_STORE_PAIR_BASE

#define A64_OP_LOAD_STORE_PAIR_BASE   (0b101000U << 24)

A64_OP_LOGICAL_REG

#define A64_OP_LOGICAL_REG   (0b01010U << 24)

A64_OP_MOVE_WIDE_IMM

#define A64_OP_MOVE_WIDE_IMM   (0b100101U << 23)

A64_OP_SYSTEM

#define A64_OP_SYSTEM   (0b11010100U << 25)

A64_OPC_ADD

#define A64_OPC_ADD   (0b00U << 29)

A64_OPC_ADDS

#define A64_OPC_ADDS   (0b01U << 29)

A64_OPC_BLR

#define A64_OPC_BLR   (0b0001U << 21)

A64_OPC_BR

#define A64_OPC_BR   (0b0000U << 21)

A64_OPC_CBNZ

#define A64_OPC_CBNZ   (1U << 24)

A64_OPC_LDP

#define A64_OPC_LDP   (0b01U << 30)

A64_OPC_MOVK

#define A64_OPC_MOVK   (0b11U << 29)

A64_OPC_MOVZ

#define A64_OPC_MOVZ   (0b10U << 29)

A64_OPC_RET

#define A64_OPC_RET   (0b0010U << 21)

A64_OPC_STP

#define A64_OPC_STP   (0b00U << 30)

A64_OPC_SUB

#define A64_OPC_SUB   (0b10U << 29)

A64_OPC_SUBS

#define A64_OPC_SUBS   (0b11U << 29)

A64_OPCODE_ORR

#define A64_OPCODE_ORR   (0b01U << 29)

A64_SF_32BIT

#define A64_SF_32BIT   (0U << 31)

A64_SF_64BIT

#define A64_SF_64BIT   (1U << 31)

A64_V_VECTOR

#define A64_V_VECTOR   (1U << 26)

Enumeration Type Documentation

arm64_gpr

enum arm64_gpr

Enumerator
X0_REG	Argument 1 / Return value / Volatile (caller-saved).
X1_REG	Argument 2 / Volatile.
X2_REG	Argument 3 / Volatile.
X3_REG	Argument 4 / Volatile.
X4_REG	Argument 5 / Volatile.
X5_REG	Argument 6 / Volatile.
X6_REG	Argument 7 / Volatile.
X7_REG	Argument 8 / Volatile.
X8_REG	Indirect result location register (holds address for large struct returns) / Volatile.
X9_REG	Volatile (caller-saved) scratch register.
X10_REG	Volatile scratch register.
X11_REG	Volatile scratch register.
X12_REG	Volatile scratch register.
X13_REG	Volatile scratch register.
X14_REG	Volatile scratch register.
X15_REG	Volatile scratch register.
X16_REG	Intra-Procedure-call scratch register (IP0) / Volatile. Linker-modifiable.
X17_REG	Intra-Procedure-call scratch register (IP1) / Volatile. Linker-modifiable.
X18_REG	Platform Register (reserved, usage is platform-specific) / May be callee-saved. Avoid use.
X19_REG	Callee-saved. Must be preserved by a called function.
X20_REG	Callee-saved.
X21_REG	Callee-saved.
X22_REG	Callee-saved.
X23_REG	Callee-saved.
X24_REG	Callee-saved.
X25_REG	Callee-saved.
X26_REG	Callee-saved.
X27_REG	Callee-saved.
X28_REG	Callee-saved.
X29_FP_REG	Frame Pointer (FP) / Callee-saved.
X30_LR_REG	Link Register (LR), holds the return address / Callee-saved by convention, but volatile on call.
SP_REG	Stack Pointer (SP). In some instructions, encoding 31 refers to the Zero Register (XZR/WZR).

arm64_vpr

enum arm64_vpr

Enumerator
V0_REG	Argument 1 / Return value / Volatile (caller-saved).
V1_REG	Argument 2 / Volatile.
V2_REG	Argument 3 / Volatile.
V3_REG	Argument 4 / Volatile.
V4_REG	Argument 5 / Volatile.
V5_REG	Argument 6 / Volatile.
V6_REG	Argument 7 / Volatile.
V7_REG	Argument 8 / Volatile.
V8_REG	Callee-saved (Note: only the lower 64 bits must be preserved).
V9_REG	Callee-saved (only lower 64 bits).
V10_REG	Callee-saved (only lower 64 bits).
V11_REG	Callee-saved (only lower 64 bits).
V12_REG	Callee-saved (only lower 64 bits).
V13_REG	Callee-saved (only lower 64 bits).
V14_REG	Callee-saved (only lower 64 bits).
V15_REG	Callee-saved (only lower 64 bits).
V16_REG	Volatile (caller-saved) scratch register.
V17_REG	Volatile scratch register.
V18_REG	Volatile scratch register.
V19_REG	Volatile scratch register.
V20_REG	Volatile scratch register.
V21_REG	Volatile scratch register.
V22_REG	Volatile scratch register.
V23_REG	Volatile scratch register.
V24_REG	Volatile scratch register.
V25_REG	Volatile scratch register.
V26_REG	Volatile scratch register.
V27_REG	Volatile scratch register.
V28_REG	Volatile scratch register.
V29_REG	Volatile scratch register.
V30_REG	Volatile scratch register.
V31_REG	Volatile scratch register.