abi_arm64_common.h

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#pragma once
#include <stdint.h>
typedef enum {
    X0_REG = 0,   
    X1_REG,       
    X2_REG,       
    X3_REG,       
    X4_REG,       
    X5_REG,       
    X6_REG,       
    X7_REG,       
    X8_REG,       
    X9_REG,       
    X10_REG,      
    X11_REG,      
    X12_REG,      
    X13_REG,      
    X14_REG,      
    X15_REG,      
    X16_REG,      
    X17_REG,      
    X18_REG,      
    X19_REG,      
    X20_REG,      
    X21_REG,      
    X22_REG,      
    X23_REG,      
    X24_REG,      
    X25_REG,      
    X26_REG,      
    X27_REG,      
    X28_REG,      
    X29_FP_REG,   
    X30_LR_REG,   
    SP_REG = 31,  
} arm64_gpr;
typedef enum {
    V0_REG = 0,  
    V1_REG,      
    V2_REG,      
    V3_REG,      
    V4_REG,      
    V5_REG,      
    V6_REG,      
    V7_REG,      
    V8_REG,      
    V9_REG,      
    V10_REG,     
    V11_REG,     
    V12_REG,     
    V13_REG,     
    V14_REG,     
    V15_REG,     
    V16_REG,     
    V17_REG,     
    V18_REG,     
    V19_REG,     
    V20_REG,     
    V21_REG,     
    V22_REG,     
    V23_REG,     
    V24_REG,     
    V25_REG,     
    V26_REG,     
    V27_REG,     
    V28_REG,     
    V29_REG,     
    V30_REG,     
    V31_REG,     
} arm64_vpr;
typedef enum {
    A64_COND_EQ = 0x0,  
    A64_COND_NE = 0x1,  
    A64_COND_CS = 0x2,  
    A64_COND_HS = 0x2,
    A64_COND_CC = 0x3,  
    A64_COND_LO = 0x3,
    A64_COND_MI = 0x4,  
    A64_COND_PL = 0x5,  
    A64_COND_VS = 0x6,  
    A64_COND_VC = 0x7,  
    A64_COND_HI = 0x8,  
    A64_COND_LS = 0x9,  
    A64_COND_GE = 0xA,  
    A64_COND_LT = 0xB,  
    A64_COND_GT = 0xC,  
    A64_COND_LE = 0xD,  
    A64_COND_AL = 0xE,  
} arm64_cond;
// Common bitfields
#define A64_SF_64BIT (1U << 31)  // 'sf' (size field) bit for 64-bit operations
#define A64_SF_32BIT (0U << 31)  // 'sf' bit for 32-bit operations
#define A64_V_VECTOR (1U << 26)  // Vector bit for SIMD/FP instructions
// Data Processing -- Immediate (e.g., ADD, SUB)
#define A64_OPC_ADD (0b00U << 29)
#define A64_OPC_ADDS (0b01U << 29)
#define A64_OPC_SUB (0b10U << 29)
#define A64_OPC_SUBS (0b11U << 29)
#define A64_OP_ADD_SUB_IMM (0b0010001U << 24)
// Data Processing -- Register (e.g., ADD, ORR)
#define A64_OP_ADD_SUB_REG (0b01011U << 24)
#define A64_OP_LOGICAL_REG (0b01010U << 24)
#define A64_OPCODE_ORR (0b01U << 29)
// Move Wide (MOVZ, MOVK)
#define A64_OPC_MOVZ (0b10U << 29)
#define A64_OPC_MOVK (0b11U << 29)
#define A64_OP_MOVE_WIDE_IMM (0b100101U << 23)
// Load/Store -- Immediate Unsigned Offset
#define A64_OP_LOAD_STORE_IMM_UNSIGNED (0b111001U << 24)
#define A64_LDR_OP (1U << 22)
#define A64_OP_LOAD_STORE_PAIR_BASE (0b101000U << 24)  // Base for all LDP/STP variants
#define A64_OPC_STP (0b00U << 30)                      // opc field for Store Pair
#define A64_OPC_LDP (0b01U << 30)                      // opc field for Load Pair
#define A64_L_BIT_LOAD (1U << 22)                      // The 'L' bit distinguishes Load (1) from Store (0)
// Addressing modes for LDP/STP
#define A64_ADDR_POST_INDEX (0b01U << 23)     // [Xn], #imm
#define A64_ADDR_PRE_INDEX (0b11U << 23)      // [Xn, #imm]!
#define A64_ADDR_SIGNED_OFFSET (0b10U << 23)  // [Xn, #imm]
// Branching
#define A64_OP_BRANCH_REG (0b1101011U << 25)
#define A64_OPC_BR (0b0000U << 21)
#define A64_OPC_BLR (0b0001U << 21)
#define A64_OPC_RET (0b0010U << 21)
#define A64_OP_COMPARE_BRANCH_IMM (0b011010U << 25)
#define A64_OPC_CBNZ (1U << 24)
// System
#define A64_OP_SYSTEM (0b11010100U << 25)
#define A64_OP_BRK (0b00000000001U << 16)
#define A64_OP_SVC (0b00000000001U << 21)